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74LVX163 Low Voltage Synchronous Binary Counter with Synchronous Clear
October 1996 Revised March 1999
74LVX163 Low Voltage Synchronous Binary Counter with Synchronous Clear
General Description
The LVX163 is a synchronous modulo-16 binary counter. This device is synchronously presettable for application in programmable dividers and has two types of Count Enable inputs plus a Terminal Count output for versatility in forming multistage counters. The CLK input is active on the rising edge. Both PE and MR inputs are active on low logic levels. Presetting is synchronous to rising edge of the CLK and the Clear function of the LVX163 is synchronous to the CLK. Two enable inputs (CEP and CET) and Carry Output are provided to enable easy cascading of counters, which facilitates easy implementation of n-bit counters without using external gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems.
Features
s Input voltage level translation from 5V to 3V s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise and dynamic threshold performance
Ordering Code:
Order Number 74LVX163M 74LVX163SJ 74LVX163MTC Package Number M16A M16D MTC16 Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names CEP CET CP MR P0-P3 PE Q0-Q3 TC Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Synchronous Master Reset Input Parallel Data Inputs Parallel Enable Inputs Flip-Flop Outputs Terminal Count Output Description
(c) 1999 Fairchild Semiconductor Corporation
DS012157.prf
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74LVX163
Functional Description
The LVX163 counts in modulo-16 binary sequence. From state 15 (HHHH) it increments to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: synchronous reset, parallel load, count-up and hold. Four control inputs--Synchronous Reset (MR), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)--determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The LVX163 uses D-type edge-triggered flip-flops and changing the MR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle takes 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. When the Parallel Enable (PE) is LOW, the parallel data outputs O0-O3 are active and follow the flip-flop Q outputs. A HIGH signal on PE forces O0-O3 to the High impedance state but does not prevent counting, loading or resetting. Logic Equations: Count Enable = CEP * CET * PE TC = Q0 * Q1 * Q2 * Q3 * CET Mode Select Table MR PE CET CEP Action on the Rising Clock Edge () L H H H H X L H H H X X H L X X X H X L Reset (Clear) Load (Pn Qn) Count (Increment) No Change (Hold) No Change (Hold)
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition
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74LVX163
State Diagram
FIGURE 1.
FIGURE 2.
Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVX163
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) Power Dissipation 50 mA -65C to +150C 180 mW 25 mA -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA -0.5V to 7V -0.5V to +7.0V
Recommended Operating Conditions (Note 2)
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Input Rise and Fall Time (t/v) 2.0V to 3.6V 0V to 5.5V 0V to VCC -40C to +85C 0 ns/V to 100 ns/V
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH Parameter HIGH Level Input Voltage VIL LOW Level Input Voltage VOH HIGH Level Output Voltage VOL LOW Level Output Voltage IIN ICC Input Leakage Current Quiescent Supply Current VCC 2.0 3.0 3.6 2.0 3.0 3.6 2.0 3.0 3.0 2.0 3.0 3.0 3.6 3.6 1.9 2.9 2.58 0.0 0.0 0.1 0.1 0.36 0.1 2.0 2.0 3.0 TA = +25C Min 1.5 2.0 2.4 0.5 0.8 0.8 1.9 2.9 2.48 0.1 0.1 0.44 1.0 20.0 A A V V Typ Max TA = -40C to +85C Min 1.5 2.0 2.4 0.5 0.8 0.8 VIN = VIL or VIH IOH = -50 A IOH = -50 A IOH = -4 mA VIN = VIL or VIH IOL = 50 A IOL = 50 A IOL = 4 mA VIN = 5.5V or GND VIN = VCC or GND V V Max Units Conditions
Noise Characteristics
Symbol VOLP (Note 3) VOLV (Note 3) VIHD (Note 3) VILD (Note 3) Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage 3.3 0.8 V 50 3.3 2.0 V 50 3.3 -0.2 -0.5 V 50 VCC (V) 3.3 TA = 25C Typ 0.2 Limits 0.5 Units V CL (pF) 50
Note 3: Parameter guaranteed by design.
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74LVX163
AC Electrical Characteristics
Symbol tPLH tPHL Parameter Propagation Delay Time (CP-Qn) 3.3 0.3 tPLH tPHL Propagation Delay Time (CP-TC, Count) 3.3 0.3 tPLH tPHL Propagation Delay Time (CP-TC, Load) 3.3 0.3 tPLH tPHL Propagation Delay Time (CET-TC) 3.3 0.3 fMAX Maximum Clock Frequency 3.3 0.3 CIN CPD Input Capacitance Power Dissipation Capacitance 2.7 75 50 80 55 2.7 2.7 2.7 VCC (V) 2.7 TA = 25C Min Typ 9.0 11.3 8.3 10.8 9.5 12.5 8.7 11.2 11.4 14.0 11.0 13.5 8.6 11.0 7.5 10.5 115 80 130 85 4 23 10 Max 14.0 17.0 12.8 16.3 14.3 18.5 13.6 17.1 18.0 21.0 17.2 20.7 13.5 16.5 12.3 15.8 TA = -40C to +85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 65 45 70 50 10 Max 16.0 19.0 15.0 18.5 16.7 20.5 16.0 19.5 21.0 24.0 20.0 23.5 15.0 18.5 14.5 18.0 Units ns ns ns ns ns ns ns ns MHz MHz pF pF Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF VCC = Open (Note 4)
Note 4: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD * VCC * fIN + ICC. When the outputs drive a capacitive load, total current consumption is the sum of CPD, and ICC which is obtained from the following formula:
CQ0-C Q3 and CTC are the capacitances at Q0-Q3 and TC, respectively. FCP is the input frequency of the CP.
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74LVX163
AC Operating Requirements
Symbol tS tS tS tS tH tH tH tH tW(L) tW(H) Minimum Setup Time (Pn-CP) Minimum Setup Time (PE -CP) Minimum Setup Time (CEP or CET-CP) Minimum Setup Time (MR -CP) Minimum Hold Time (Pn-CP) Minimum Hold Time (PE -CP) Minimum Hold Time (CEP or CET-CP) Minimum Hold Time (MR -CP) Minimum Pulse Width CP (Count) Parameter VCC (V) 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 TA = 25C TA = -40C to +85C Units Guaranteed Minimum 5.5 5.5 8.0 8.0 7.5 7.5 4.0 4.0 1.0 1.0 1.0 1.0 1.0 1.0 1.5 1.5 5.0 5.0 6.5 6.5 9.5 9.5 9.0 9.0 4.0 4.0 1.0 1.0 1.0 1.0 1.0 1.0 1.5 1.5 5.0 5.0
ns ns ns ns ns ns ns ns ns
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74LVX163
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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74LVX163 Low Voltage Synchronous Binary Counter with Synchronous Clear
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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